Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors 


Vol. 38,  No. 10, pp. 852-857, Oct.  2013


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  Abstract

In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

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  Cite this article

[IEEE Style]

S. Ahn, S. Lim, Y. Yang, K. Yang, "Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 10, pp. 852-857, 2013. DOI: .

[ACM Style]

Seok-Ki Ahn, Seung-Chan Lim, Youngoh Yang, and Kyeongcheol Yang. 2013. Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors. The Journal of Korean Institute of Communications and Information Sciences, 38, 10, (2013), 852-857. DOI: .

[KICS Style]

Seok-Ki Ahn, Seung-Chan Lim, Youngoh Yang, Kyeongcheol Yang, "Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors," The Journal of Korean Institute of Communications and Information Sciences, vol. 38, no. 10, pp. 852-857, 10. 2013.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880