Design of a Low Power 10bit Flash SAR A/D Converter 


Vol. 40,  No. 4, pp. 613-618, Apr.  2015


PDF Full-Text
  Abstract

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes 136μW with a power supply of 1V under a 0.18μm CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

  Statistics
Cumulative Counts from November, 2022
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.


  Cite this article

[IEEE Style]

G. Lee, J. Kim, K. Yoon, "Design of a Low Power 10bit Flash SAR A/D Converter," The Journal of Korean Institute of Communications and Information Sciences, vol. 40, no. 4, pp. 613-618, 2015. DOI: .

[ACM Style]

Gi-Yoon Lee, Jeong-Heum Kim, and Kwang-Sub Yoon. 2015. Design of a Low Power 10bit Flash SAR A/D Converter. The Journal of Korean Institute of Communications and Information Sciences, 40, 4, (2015), 613-618. DOI: .

[KICS Style]

Gi-Yoon Lee, Jeong-Heum Kim, Kwang-Sub Yoon, "Design of a Low Power 10bit Flash SAR A/D Converter," The Journal of Korean Institute of Communications and Information Sciences, vol. 40, no. 4, pp. 613-618, 4. 2015.

Search
(IN TITLE, AUTHOR, ABSTRACT,KEYWORDS)

Advanced Search ▼

POPULAR KEYWORDS
(TOP 10 KEYWORDS)

Recent Publications
(LAST 3 YEARS)






pISSN : 1226 - 4717
eISSN : 2287 - 3880