High-Speed Intra Prediction VLSI Implementation for HEVC 


Vol. 41,  No. 11, pp. 1502-1506, Nov.  2016


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  Abstract

HEVC (High Efficiency Video Coding) is a recently proposed video compression standard that has a two times greater coding efficiency than previous video compression standards. The key factors of high compression performance and increasement of computational complexity are the various types of block partitions and modes of intra prediction in HEVC. This paper presents an intra prediction hardware architecture for HEVC utilizing pipelining and interleaving techniques to increase the efficiency and performance while reducing the requirement for hardware resources.

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  Cite this article

[IEEE Style]

H. Jo, Y. Hong, H. Jang, "High-Speed Intra Prediction VLSI Implementation for HEVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 41, no. 11, pp. 1502-1506, 2016. DOI: .

[ACM Style]

Hyeonsu Jo, Youpyo Hong, and Hanbeyoul Jang. 2016. High-Speed Intra Prediction VLSI Implementation for HEVC. The Journal of Korean Institute of Communications and Information Sciences, 41, 11, (2016), 1502-1506. DOI: .

[KICS Style]

Hyeonsu Jo, Youpyo Hong, Hanbeyoul Jang, "High-Speed Intra Prediction VLSI Implementation for HEVC," The Journal of Korean Institute of Communications and Information Sciences, vol. 41, no. 11, pp. 1502-1506, 11. 2016.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880