Design of a 10Bit Comparison Register A/D Converter with 2Bit/Step and Threshold Configuring Comparator 


Vol. 42,  No. 9, pp. 1719-1725, Sep.  2017
10.7840/kics.2017.42.9.1719


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  Abstract

This paper proposed a 10 bir SAR A/D converter with 2bit/step and Threshold Configuring Comparator. The structure of the entire circuit is composed of a Threshold Configuring Comparator for the 5MSBs and a 5LSBs capacitor D/A converter, reducing the number of capacitors and power consumption. By using a clock doubling circuit that halves the clock cycle, 2 bits were determined for each step to increase the conversion speed. The proposed A/D converter is fabricated using a 0.18 μm CMOS process and has a conversion speed of 10 MS/s. A 9.5 bit ENOB(effective number of bit) is measured, INL / DNL are ±1 / 0.5LSB, chip area and power consumption are 750x700 μ㎡ and 56 μW respectively, and FoM has 7.73fJ/step.

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  Cite this article

[IEEE Style]

S. Lee, H. Lee, K. Yoon, "Design of a 10Bit Comparison Register A/D Converter with 2Bit/Step and Threshold Configuring Comparator," The Journal of Korean Institute of Communications and Information Sciences, vol. 42, no. 9, pp. 1719-1725, 2017. DOI: 10.7840/kics.2017.42.9.1719.

[ACM Style]

Sang-Heon Lee, Ho-Yong Lee, and Kwang-Sub Yoon. 2017. Design of a 10Bit Comparison Register A/D Converter with 2Bit/Step and Threshold Configuring Comparator. The Journal of Korean Institute of Communications and Information Sciences, 42, 9, (2017), 1719-1725. DOI: 10.7840/kics.2017.42.9.1719.

[KICS Style]

Sang-Heon Lee, Ho-Yong Lee, Kwang-Sub Yoon, "Design of a 10Bit Comparison Register A/D Converter with 2Bit/Step and Threshold Configuring Comparator," The Journal of Korean Institute of Communications and Information Sciences, vol. 42, no. 9, pp. 1719-1725, 9. 2017. (https://doi.org/10.7840/kics.2017.42.9.1719)

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pISSN : 1226 - 4717
eISSN : 2287 - 3880