The Design of Phase error Detector Based on Delayed n-Tap Rising Edge Clock : It's DP-PLL System Application
Vol. 23, No. 4, pp. 1100-1112, Apr. 1998
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Cite this article
[IEEE Style]
박군종, 구광일, 윤정현, 윤대희, 차일환, "The Design of Phase error Detector Based on Delayed n-Tap Rising Edge Clock : It's DP-PLL System Application," The Journal of Korean Institute of Communications and Information Sciences, vol. 23, no. 4, pp. 1100-1112, 1998. DOI: .
[ACM Style]
박군종, 구광일, 윤정현, 윤대희, and 차일환. 1998. The Design of Phase error Detector Based on Delayed n-Tap Rising Edge Clock : It's DP-PLL System Application. The Journal of Korean Institute of Communications and Information Sciences, 23, 4, (1998), 1100-1112. DOI: .
[KICS Style]
박군종, 구광일, 윤정현, 윤대희, 차일환, "The Design of Phase error Detector Based on Delayed n-Tap Rising Edge Clock : It's DP-PLL System Application," The Journal of Korean Institute of Communications and Information Sciences, vol. 23, no. 4, pp. 1100-1112, 4. 1998.
pISSN : 1226 - 4717
eISSN : 2287 - 3880