Design of a 5.2㎓/2.4㎓ Dual band CMOS Frequency Synthesizer for WLAN 


Vol. 32,  No. 1, pp. 134-141, Jan.  2007


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  Abstract

This paper presents a frequency synthesizer(FS) for 5.2㎓/2.4㎓ dual band wireless applications which is designed in a standard 0.18㎛ CMOS1P6M process. The 2.4㎓ frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700㎒ and the locking time is 4㎲. The simulated phase noise of PLL is -101.36㏈c/㎐ at 200㎑ offset frequency from 5.0㎓ with SCA circuit on.

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  Cite this article

[IEEE Style]

K. Kim, S. Lee, K. Yoon, S. Kim, "Design of a 5.2㎓/2.4㎓ Dual band CMOS Frequency Synthesizer for WLAN," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 1, pp. 134-141, 2007. DOI: .

[ACM Style]

Kwang-il Kim, Sang-Cheol Lee, Kwang-Sub Yoon, and Seok-jin Kim. 2007. Design of a 5.2㎓/2.4㎓ Dual band CMOS Frequency Synthesizer for WLAN. The Journal of Korean Institute of Communications and Information Sciences, 32, 1, (2007), 134-141. DOI: .

[KICS Style]

Kwang-il Kim, Sang-Cheol Lee, Kwang-Sub Yoon, Seok-jin Kim, "Design of a 5.2㎓/2.4㎓ Dual band CMOS Frequency Synthesizer for WLAN," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 1, pp. 134-141, 1. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880