Efficient pipelined FFT processor for the MIMO-OFDM systems 


Vol. 32,  No. 10, pp. 1025-1031, Oct.  2007


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  Abstract

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS 0.18㎛ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.

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  Cite this article

[IEEE Style]

S. Lee, Y. Jung, J. Kim, "Efficient pipelined FFT processor for the MIMO-OFDM systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1025-1031, 2007. DOI: .

[ACM Style]

Sangmin Lee, Yunho Jung, and Jaeseok Kim. 2007. Efficient pipelined FFT processor for the MIMO-OFDM systems. The Journal of Korean Institute of Communications and Information Sciences, 32, 10, (2007), 1025-1031. DOI: .

[KICS Style]

Sangmin Lee, Yunho Jung, Jaeseok Kim, "Efficient pipelined FFT processor for the MIMO-OFDM systems," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 10, pp. 1025-1031, 10. 2007.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880