A Performance Evaluation Method of Digital FIR Matched Filter Implemented by Hardware Reduction Method 


Vol. 32,  No. 12, pp. 371-376, Dec.  2007


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  Abstract

In oerder to reduce hardware of digital FIR matched filter, the filter coefficients can be represented by the powers of 2 with the minimum number of digit. The digital filter whilch coefficients are represented by the powers of 2 would have many advantage when it is FPGA implemented, because the implemented hardware can operate multiplication simply by shift. Especially, due to the simple structure, FPGA filter can cope with the very high sampling rate in the digital radio range. However, in the case of FPGA filter implementation, the performance evaluation method would be required for reasons of coefficients register bit limitation, the coefficients distortion for hardware reduction, and so on. In this paper, FIR matched filter is designed through hardware reduction method, and the performance evaluation method is proposed.

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  Cite this article

[IEEE Style]

S. Lee, "A Performance Evaluation Method of Digital FIR Matched Filter Implemented by Hardware Reduction Method," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 371-376, 2007. DOI: .

[ACM Style]

Sang-Cheol Lee. 2007. A Performance Evaluation Method of Digital FIR Matched Filter Implemented by Hardware Reduction Method. The Journal of Korean Institute of Communications and Information Sciences, 32, 12, (2007), 371-376. DOI: .

[KICS Style]

Sang-Cheol Lee, "A Performance Evaluation Method of Digital FIR Matched Filter Implemented by Hardware Reduction Method," The Journal of Korean Institute of Communications and Information Sciences, vol. 32, no. 12, pp. 371-376, 12. 2007.