An I/Q Channel 12bit 40MS/s Pipeline A/D Converter with DLL Based Duty-Correction Circuit for WLAN 


Vol. 33,  No. 5, pp. 395-402, May  2008


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  Abstract

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a 0.18㎛ CMOS n-well 1-poly 6-metal process and dissipates 184㎽ at 1.8V single supply. The SNDR of the proposed 12bit ADC is 52㏈ and SFDR of 59dBc (@Fs=20㎒, Fin=1㎒) is measured.

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  Cite this article

[IEEE Style]

J. Lee, S. Cho, H. Park, S. Lee, K. Yoon, "An I/Q Channel 12bit 40MS/s Pipeline A/D Converter with DLL Based Duty-Correction Circuit for WLAN," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 395-402, 2008. DOI: .

[ACM Style]

Jae-yong Lee, Sung-il Cho, Hyun-mook Park, Sang-min Lee, and Kwang-sub Yoon. 2008. An I/Q Channel 12bit 40MS/s Pipeline A/D Converter with DLL Based Duty-Correction Circuit for WLAN. The Journal of Korean Institute of Communications and Information Sciences, 33, 5, (2008), 395-402. DOI: .

[KICS Style]

Jae-yong Lee, Sung-il Cho, Hyun-mook Park, Sang-min Lee, Kwang-sub Yoon, "An I/Q Channel 12bit 40MS/s Pipeline A/D Converter with DLL Based Duty-Correction Circuit for WLAN," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 5, pp. 395-402, 5. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880