Study of a Low-power Error Correction Circuit for Image Processing 


Vol. 33,  No. 10, pp. 798-804, Oct.  2008


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  Abstract

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

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  Cite this article

[IEEE Style]

S. Lee, J. Park, H. Jeon, Y. Lee, "Study of a Low-power Error Correction Circuit for Image Processing," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 10, pp. 798-804, 2008. DOI: .

[ACM Style]

Sang-jun Lee, Jong-su Park, Ho-yun Jeon, and Yong-surk Lee. 2008. Study of a Low-power Error Correction Circuit for Image Processing. The Journal of Korean Institute of Communications and Information Sciences, 33, 10, (2008), 798-804. DOI: .

[KICS Style]

Sang-jun Lee, Jong-su Park, Ho-yun Jeon, Yong-surk Lee, "Study of a Low-power Error Correction Circuit for Image Processing," The Journal of Korean Institute of Communications and Information Sciences, vol. 33, no. 10, pp. 798-804, 10. 2008.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880