Performance Evaluation of Secure Embedded Processor using FEC-Based Instruction-Level Correlation Technique 


Vol. 34,  No. 5, pp. 526-531, May  2009


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  Abstract

In this paper, we propose new novel technique (ILCT: Instruction-Level Correlation Technique) which can detect tempered instructions by software attacks or hardware attacks before their execution. In conventional works, due to both high complex computation of cipher process and low processing speed of cipher modules, existing secure processor architecture applying cipher technique can cause serious performance degradation. While, the secure processor architecture applying ILCT with FEC does not incur excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, total memory overhead including parity are increased in average of 26.62%. Also, secure programs incur CPI degradation in average of 1.20%~1.97%.

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  Cite this article

[IEEE Style]

S. W. Lee, S. Kwon, J. T. Kim, "Performance Evaluation of Secure Embedded Processor using FEC-Based Instruction-Level Correlation Technique," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 5, pp. 526-531, 2009. DOI: .

[ACM Style]

Seung Wook Lee, Soongyu Kwon, and Jong Tae Kim. 2009. Performance Evaluation of Secure Embedded Processor using FEC-Based Instruction-Level Correlation Technique. The Journal of Korean Institute of Communications and Information Sciences, 34, 5, (2009), 526-531. DOI: .

[KICS Style]

Seung Wook Lee, Soongyu Kwon, Jong Tae Kim, "Performance Evaluation of Secure Embedded Processor using FEC-Based Instruction-Level Correlation Technique," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 5, pp. 526-531, 5. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880