Silicon Thickness Control and Laser sawing to Reduce Scribe lane in COG Package 


Vol. 34,  No. 6, pp. 164-168, Jun.  2009


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  Abstract

The purpose of this study is to analyze the method for eliminating chipping occurred on The surface of semiconductor in production line, and to improve the net die problem, for this purpose, I suggest solutions for chipping and net die of serious problems as follows. Laser sawing can be the most damaging step in semiconductor manufacturing where individual dice are freed from a brittle silicon wafer. We have experimented a DDI device using silicon wafers cut to ＞0.2㎜ long 0.02 ㎜ wide and 180 ㎛ thick. We try design equipment with these two kinds solution and co work with equipment manufacture. SEM (scanning electron microscope) was used to the analyze failure mechanics. The degradation of chipping of laser sawing caused by wafer thickness and size of test pattern was discussed.

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  Cite this article

[IEEE Style]

K. Kim and H. Lee, "Silicon Thickness Control and Laser sawing to Reduce Scribe lane in COG Package," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 6, pp. 164-168, 2009. DOI: .

[ACM Style]

Kyeong-Su Kim and Ho-Woong Lee. 2009. Silicon Thickness Control and Laser sawing to Reduce Scribe lane in COG Package. The Journal of Korean Institute of Communications and Information Sciences, 34, 6, (2009), 164-168. DOI: .

[KICS Style]

Kyeong-Su Kim and Ho-Woong Lee, "Silicon Thickness Control and Laser sawing to Reduce Scribe lane in COG Package," The Journal of Korean Institute of Communications and Information Sciences, vol. 34, no. 6, pp. 164-168, 6. 2009.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880