900㎒ RFID Passive Tag Frontend Design and Implementation 


Vol. 35,  No. 7, pp. 1081-1090, Jul.  2010


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  Abstract

0.18㎛ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77㎟ ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about 71㎼.

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  Cite this article

[IEEE Style]

J. Hwang, J. H. Oh, H. Kim, D. Lee, H. Roh, Y. Seong, H. Oh, J. Park, "900㎒ RFID Passive Tag Frontend Design and Implementation," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 7, pp. 1081-1090, 2010. DOI: .

[ACM Style]

Ji-Hun Hwang, Jong Hwa Oh, Hyun-Woong Kim, Dong-Gun Lee, Hyoung-Hwan Roh, Yeong-rak Seong, Ha-ryoung Oh, and Jun-seok Park. 2010. 900㎒ RFID Passive Tag Frontend Design and Implementation. The Journal of Korean Institute of Communications and Information Sciences, 35, 7, (2010), 1081-1090. DOI: .

[KICS Style]

Ji-Hun Hwang, Jong Hwa Oh, Hyun-Woong Kim, Dong-Gun Lee, Hyoung-Hwan Roh, Yeong-rak Seong, Ha-ryoung Oh, Jun-seok Park, "900㎒ RFID Passive Tag Frontend Design and Implementation," The Journal of Korean Institute of Communications and Information Sciences, vol. 35, no. 7, pp. 1081-1090, 7. 2010.

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pISSN : 1226 - 4717
eISSN : 2287 - 3880