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Effective Decoding Algorithm of Three dimensional Product Code Decoding Scheme with Single Parity Check Code
Sang-chul Ha  Byung-kyu Ahn  Ji-myung Oh  Do-kyoung Kim  Jun Heo

Vol. 41, No. 9, pp. 1095-1102, Sep. 2016

Hardware-Based High Performance XML Parsing Technique Using an FPGA
Kyu-hee Lee  Byeong-seok Seo
Vol. 40, No. 12, pp. 2469-2475, Dec. 2015

Design and Implementation of High-Speed Pattern Matcher Using Multi-Entry Simultaneous Comparator in Network Intrusion Detection System
Myung-Jae Jeon  Sun-Young Hwang
Vol. 40, No. 11, pp. 2169-2177, Nov. 2015

A Gigabit Serial Transceiver Design Using FPGA for Satellite Communication Transponder
Keun-Pyo Hong  Jung-Sub Lee  Byoung-Il Jin  Hyun-Suk Ko  Hak-Geum Seo

Vol. 39, No. 8, pp. 481-487, Aug. 2014

Development and Verification of Digital EEG Signal Transmission Protocol
Do-Hoon Kim  Kyu-Sung Hwang
Vol. 38, No. 7, pp. 623-629, Jul. 2013

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pISSN : 1226 - 4717
eISSN : 2287 - 3880