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Improved Performance Decoding for LDPC Codes with a Large Number of Short Cycles
Kyuhyuk Chung
Vol. 33, No. 2, pp. 173-177, Feb. 2008

Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems
Hyeong-Gun Joo  Dong-Joon Shin  Song-Nam Hong
Vol. 32, No. 12, pp. 1135-1141, Dec. 2007

Split LDPC Codes for Hybrid ARQ
Hyeong-Gun Joo  Song-Nam Hong  Dong-Joon Shin
Vol. 32, No. 10, pp. 942-949, Oct. 2007

Performance Improvement in High SNR for LDPC codes using Power Allocation
Kijun Lee  Habong Chung  Juhyuk Im  Eun-A Choi  Dae-Ig Chang

Vol. 32, No. 10, pp. 935-941, Oct. 2007

Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations
Jun-Ho Lee  Chang-Soo Park  Sun-Young Hwang
Vol. 32, No. 9, pp. 801-809, Sep. 2007

Low Density Parity Check Codes for Hybrid ARQ System
Woo Tae Kim  Jeong Goo Kim  Eon Kyeong Joo
Vol. 32, No. 4, pp. 370-378, Apr. 2007

Decoding Method of LDPC Codes in IEEE 802.16e Standards for Improving the Convergence Speed
Min-Ho Jang  Beom-Kyu Shin  Woo-Myoung Park  Jong-Seon No  In-San Jeon

Vol. 31, No. 12, pp. 1143-1149, Dec. 2006

Interleaver Design of Punctured RA-Type LDPC Codes
Yong-Chun Piao  Dong-Joon Shin
Vol. 31, No. 12, pp. 1129-1134, Dec. 2006

Construction of Optimal Concatenated Zigzag Codes Using Density Evolution with a Gaussian Approximation
Song-Nam Hong  Dong-Joon Shin
Vol. 31, No. 9, pp. 825-830, Sep. 2006

New Message-Passing Decoding Algorithm of LDPC Codes by Partitioning Check Nodes
Sunghwan Kim  Min-Ho Jang  Jong-Seon No  Song-Nam Hong  Dong-Joon Shin

Vol. 31, No. 4, pp. 310-317, Apr. 2006

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pISSN : 1226 - 4717
eISSN : 2287 - 3880